🏗 Computer Architecture - hello · Scour

[Benchmark] C vs. Python 1GB Allocation: 17x Lower CPU Overhead (I/O Bottleneck Analysis) ⚙️Performance Profiling

github.com·3d·r/cpp·

KVSculpt: KV Cache Compression as Distillation ⏪Deoptimization

arxiv.org·2d·

Linux and RISC-V by 2030 ⚡RISC-V

lemmy.ml·19h·

bunnie's blog 🧵Lightweight Threads

bunniestudios.com·2h·

RISC-V Now! — Where Specification Meets Scale! ⚡RISC-V

semiwiki.com·2d·

The Pipeline Problem 📈Differential Dataflow

modular.com·3d·Hacker News·

WheatForce: Learning From CPU Architecture Mistakes ⚙️CPU Microarchitecture

hackaday.com·1d·

'Performance without compromise': AMD debuts first dual 3D V-Cache Ryzen CPU in potential showdown against Threadripper and EPYC siblings ⚡Hardware Acceleration

techradar.com

·1d·

6o6 v1.1: Faster 6502-on-6502 virtualization for a C64/Apple II Apple-1 emulator 🖥️Emulation

oldvcr.blogspot.com·4d·Lobsters, Hacker News, oldvcr.blogspot.com·

The Parallel Lanes Nobody Uses 🛣️Highway

dev.to·1d·DEV·

Theory of Constraints in a Go Pipeline 🔵Go

binaryphile.com·4d·

RVCC Proposed As An LLVM Incubator For High Performance RISC-V Optimizations 🔨LLVM

phoronix.com·3d·

Physical Design of UET-RVMCU: A Streamlined Open-Source RISC-V Microcontroller ⚡RISC-V

arxiv.org·2d·

NaQeEb313/BareMetal_Risc_cpu: Designed a bare-metal multi-cycle CPU, upgraded from an 8-bit base architecture to a custom 32-bit RISC processor ⚙️CPU Microarchitecture

github.com·4d·r/cpp·

SISA: A Scale-In Systolic Array for GEMM Acceleration ⚡Hardware Acceleration

arxiv.org·1d·

Peterc3-dev/rag-race-router: R.A.G-Race-Router [Adaptive Tri-Processor Inference Runtime] — Self-optimizing CPU+iGPU+NPU inference for AMD Ryzen AI 300 series ⚡Hardware Acceleration

github.com·3d·Hacker News·

Loop Control Management in Tightly Coupled Processor Arrays (TCPAs) 🗺️Memory-Mapped Queues

arxiv.org·2d·

KV Cache Quantization for Self-Forcing Video Generation: A 33-Method Empirical Study 🌊Memory Bandwidth

arxiv.org·2d·

IsoQuant: Hardware-Aligned SO(4) Isoclinic Rotations for LLM KV Cache Compression ⚙️CPU Microarchitecture

arxiv.org·2d·

Toward a Universal GPU Instruction Set Architecture: A Cross-Vendor Analysis of Hardware-Invariant Computational Primitives in Parallel Processors ⚡Hardware Acceleration

arxiv.org·1d·

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